The present invention relates generally to a cut-only CMOS switch for discretionary connect and disconnect, and more particularly to wafer-scale integrated (WSI) or restructurable very-large-scale integrated (RVLSI) CMOS circuitry, wherein redundant circuit elements are used to replace defective ones so as to achieve a fully functional die.
U.S. patents of interest include U.S. Pat. No. 4,691,078 to Nishioka et al, which shows use of a cutting technique in an aluminum circuit in order to replace defective bits by redundant bits. Coontz et al, in U.S. Pat. No. 4,092,733, selectively connect and disconnect elements on a wafer. The device of this patent is described as useful in wafer scale integration involving redundant circuitry whereby defective elements are disabled and operable elements are substituted for them. Yoshida et al, in U.S. Pat. No. 4,614,881, describe a CMOS switch for redundancy substitution on a semiconductor memory chip. The circuit of this patent is designed to reduce power consumption. McAdams, in U.S. Pat. No. 4,621,078, discloses a low power CMOS fuse circuit; and Rung, in U.S. Pat. No. 4,605,872, is concerned with a programmable CMOS disconnect circuit in a redundant element system. A pull-up circuit is shown in Van Den Crommenacher et al U.S. Pat. No. 4,577,123.